Submissions

• DAC-99 Modelling Hardware in Multiclock Esterel 36th Design Automation Conference, New Orleans, June 21 - 25, 1999
• Thesis Programming Languages: Specification and Design of Multiple Clocked Systems School of Technology and Computer Science, T.I.F.R., 1998

Publications

• Refereed Publications (Journals/Proceedings/Conferences)
• pdcn97An Implementation of Communicating Reactive Processes IASTED - PDCN'97, Int. Conf. on Parallel and Distributed Computing and Networks, Singapore, 1997
• ijhsc96 Mapping Linear Recurrence Equations onto Systolic Architectures - Intl. J. of High Speed Computing, Vol. 8, No. 3 (1996) p229-270
• ipps96 Mapping Linear recurrences onto Systolic Arrays - Intl. Parallel Processing Symposium, Hawaii, 1996
• TCS-95-10 Networks of Preemptible Reactive Processes: An Implementation - Intl. Conference on High Performance Computing, New Delhi, 1995
• TCS-94-7 Designing Systolic Architecture for Symmetrizing Hessenberg Matrices - SACAI, Kalpakkam, 1995
• TCS-94-6 An Implementation of CRP - SACAI, Kalpakkam, 1995
• icpp94 Derivation of Systolic Programs - Proc. of the Intl. Conf. on Parallel Processing, Illinois, 1994


• Workshops
• Multiclock Esterel : International Workshop on Specification and Verification, Hyderabad, India, 1996.


• Technical Reports
• TCS-95-7 An Implementation of Communicating Reactive Processes
• TCS-95-8 Mapping Linear Recurrences into Systolic Architectures
• TCS-94-3 Mapping Linear Recurrences onto Systolic Architectures