(click here for the Formal Methods in India page.) (click here for the mu M Indian Classical Music project)
Paritosh K. Pandya
Vitae and List
of Publications are accessible in postscript form and through
Bibliometric indices and citations to my papers as recorded by Google scholar.
University of Oxford: Two Variable Logics with a Between Predicate, 3rd March, 2020. (Slides)
University of Edinburgh: Logical Specification and Uniform Synthesis of Robust Controllers, 25th February, 2020. (Slides)
GANDALF 20 Conferrence: Specification and Optimal Reactive Synthesis of Runtime Enforcement Shields. (Slides)
International Logic Colloquium: Expressive Completeness and Decidability of Metric Temporal Logics, Udine, Italy, 28 July 2018.
PC Co-Chair: FSTTCS 2018, Ahmedabad, 2018.
OC Chair: POPL 2015, TIFR, Mumbai, 2015.
PC Member: HSCC 2020, LATA2018, FSTTCS 2017, PEC 2016, TIME 2016,
ICLA 2015, SETTA 2015, TASE 2015, RP 2014, SETTA 2014, TASE 2014, ICTAC 2014,
ICTAC 2013, ICDCN 2013, HSCC 2012, TIME 2011, FSTTCS 2010, TIME 2010, ICTAC 2010,
Logics, Automata, Concurrency, Formal Methods, Embedded Systems and Software Engineering.
Robust Controller Synthesis
Metric Temporal Logics and Timed automata
Duration Calculus and Model Checking
Refinement Algebra and CSP
Hoare Logics for Distributed Programs
v1.0: Guided Reactive Synthesis with Soft Requirements for
Robust Controller and Shield Synthesis.
Latest Version: DCSYNTH v1.0 released on 23 October, 2017.
a validity checker for Duration Calculus (QDDC) formulae. DCVALID
Version 1.4 includes CTLDC, a model checker for CTL extended
with past and timing properties. It checks Verilog, SMV, ESTEREL and
Lustre designs. Click for an overview
and an example.
Latest: Version 1.4 of DCVALID released on 2 October, 2000.
Aspects of Computing , The
international Journal of Formal Methods, Springer (1996-2010)
Automata and computability, (2015-2019, 2010-2013, 2008, 2007)
Formal Verification for VLSI Design, (IIT Mandi, April 2018, May 2019)
Advanced Automata Theory (Reading Course, 2018)
Foundations of Program Verification (August-December 2007)
Algebraic Automata Theory (Reading Course, 2017)
Synchronous Programming (Module in Embedded Systems Course, IIT Bombay, 2018, 2017, 2016).
Automata and Verification (Jan-Apr 2006)
Introduction to Logic (August-December, 2005.)
Automata and Computability (Aug 2003-Jan 2003)
Model Checking: Theory and Practice (Aug 2002- Jan 2003)
Automata and Computability (Aug-Dec 2001)
Introduction to Logic (Aug-Dec 1999)
Model checking : Theory and Practice (Jan-Apr 1999)
Elementary Predicate Logic (Aug-Dec 1998, Aug-Dec 1996)
Science of Programming (Aug-Dec 1994)
K. Narayan Kumar
P. Vijay Suman
Amol Wakankar (Ongoing)
M Project: Measuring Hidustani Classical Music.
(NEW A Tabla Synthesizer
Synthesis of Aalaps )
Last modified by Paritosh Pandya on 08 May, 2017.