Links:

• GM sponsored R&D project
• Technical Reports

Publications:

• Model Checking based Analysis of End-to-end Latency in Embedded, Real-time Systems with Clock Drifts. Swarup Mohalik, A. C. Rajeev, Manoj G. Dixit, S. Ramesh, P. Vijay Suman, Paritosh K. Pandya, and Shengbing Jiang. DAC ’08: Proceedings of Design Automaton Conference, 2008.
  ABSTRACT | ACM Link | Slides | Technical Report
• Timed Automata with Integer Resets: Language Inclusion and Expressiveness. P. Vijay Suman, Paritosh K. Pandya, Shankara Narayanan Krishna and Lakshmi Manasa. FORMATS ’08: Proceedings of Formal Modelling and Analysis of Timed Systems, 2008.
  ABSTRACT | Springer Link | Slides | Technical Report
• Timed and Hybrid Automata in SAL. P. Vijay Suman and Paritosh K. Pandya. RTES' 08: Real Time and Embedded Systems, 2008.
  ABSTRACT | Slides | Technical Report
• Determinization and Expressiveness of Integer Reset Timed Automata with Silent Transitions. P. Vijay Suman and Paritosh K. Pandya. LATA'09: Language and Automata Theory and Applications, 2009.
  ABSTRACT | Springer Link | Slides | Technical Report

Presentations:

• Presentation to VSRP students, 2005
• Undecidability of Universality of Timed Automata
• Impressive Power of Stopwatch Automata (Cassez et al) at Formal Methods Update Meeting, IIT Bombay, 2005
• Talks on the survey report on Foundations Of Timed And Hybrid Automata at GM R&D India Science Labs, Bangalore, December, 2006
• Determinization of Timed Automata with Integral Resets, STCS Day, 2008
• Determinization and Expressive Power of Integer Reset Timed Automata with Silent Transitions, Workshop on Automata, Concurrency and Timed Systems, CMI, 2009
• Synopsis Presentation, February 3rd, 2009
• Determinization and Expressiveness of Integer Reset Timed Automata with Silent Transitions, STCS Symposium, 2009
• Determinization and Expressiveness of Integer Reset Timed Automata with Silent Transitions, Language and Automata Theory and Applications, Tarragona, Spain, 2009.

My Documents:

• Ph.D. Thesis Synopsis