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UID:www.tcs.tifr.res.in/event/322
DTSTAMP:20230914T125919Z
SUMMARY:Next-Generation Security and Architecture
DESCRIPTION:Speaker: Prof. Steven Lumetta & Prof. Ravishankar Iyer (Univers
 ity of Illinois at Urbana-Champaign\n255 Coordinated Science Lab\, MC 228\
 n1308 W. Main St.\nUrbana\, Illinois 6180\nUnited States of America)\n\nAb
 stract: \nThe next major innovations in computer science and engineering a
 re likely to come from [UTF-8?]“intelligent” deployment of hum
 an-centric systems that must optimally interact with other man-made and na
 tural systems with a focus on seamless availability of dynamic decision-ma
 king capabilities. The compelling driver is our need to measure\, model\, 
 communicate and manage our vast natural and social enterprise. New innovat
 ion and creative approaches are essential to be able to handle problems of
  scale and complexity envisioned in this future. This change is being driv
 en by inexpensive technology deployed at previously unimaginable scales. O
 ur planet itself\, via a vast and varied network\, is generating or has th
 e potential to generate an unprecedented level of information that we were
  previously oblivious to and could ignore - we were not able or hear it\, 
 to see it or to capture it. The vast and dynamic information gathered with
  these information networks could be analyzed using powerful yet ubiquitou
 s systems- that are yet to be invented.  In this seminar Professors Iyer 
 and Lumetta will discuss two projects at the University of Illinois that i
 n their unique ways address this [UTF-8?]“big [UTF-8?]data” pr
 oblem.\n\nProfessor Iyer will address the issue of protecting a system fro
 m accidental errors and malicious attacks via a new approach based on [UTF
 -8?]“execution under [UTF-8?]probation”.  Via a combination o
 f continuous monitoring and leveraging Virtual Machines\, the method can b
 oth identify and sequester a potential attacker while ensuring that any co
 nsequent system corruption is contained.\n\nProf. Lumetta will discuss the
  development of combined software and hardware coherence protocols in the 
 context of Rigel\, a 1000-core accelerator chip.  Dynamically shifting re
 gions of memory between these two types of coherence both offers a mechani
 sm to support the two models now dominant in the industry and simplifies t
 he process of parallelizing applications for many-core execution.\n
URL:https://www.tcs.tifr.res.in/web/events/322
DTSTART;TZID=Asia/Kolkata:20121127T160000
DTEND;TZID=Asia/Kolkata:20121127T170000
LOCATION:AG-66 (Lecture Theatre)
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