Conventional shrinking methods to improve VLSI chip performance by continual scaling of device and interconnect geometries may allow CMOS juggernaut to reach about 22 nm nodes. During the post-shrinking era, a host of nanoscale technologies such as quantum tunneling devices, plasmon based transistors, ionic transport based crossbar structures, carbon nano-tube s, grapheme s, self- assembled array of quantum dots, spin-polarized magnetic tunneling junction devices, and molecular transistors are likely to emerge as commercially viable technologies that will sustain the demands for exponential economic growth throughout the present millennium.
Quantum tunneling in nanometric devices augurs a revolutionary shift of paradigm for circuit and CAD tools design that must account for quantum effects as well as local interactions between self- assembled circuit elements. These circuit elements may consist of a 2-dimensional array of self-organized quantum dots that can be instrumented to perform cellular automata class of algorithms or a 3-dimensional array of self-organized nanowires to perform a random Boolean network (RBN) class of algorithms. The talk will briefly introduce several Boolean and neuromorphic nanoarchitectures consisting of 2-D array of amorphous-Silicon based memristor devices, stress-assisted spin polarized nanomagnets, and surface plasmon polariton (SPP) based THz active and passive devices.
Biography: Professor Pinaki Mazumder received his PhD in Electrical and Computer Engineering from the University of Illinois at Urbana-Champaign in 1988. Prior to that, he received his MS degree in Computer Science from University of Alberta in Canada, BS degree in Electrical Engineering from Indian Institute of Science at Bangalore, and BSc Physics Honors degree from Guwahati University in India. Currently, he is a Professor of Electrical Engineering and Computer Science at the University of Michigan where he has been teaching for the past 24 years. He spent three years at National Science Foundation serving as the lead Program Director of Emerging Technologies Program in the CISE Directorate as well as leading the Quantum, Molecular, and High Performance Simulation Program in the Engineering Directorate. He had worked for six years in industrial R&D laboratories which included AT&T Bell Laboratories, where he started the first C language based modeling techniques for VLSI synthesis tool in 1985. Professor Mazumder spent his sabbatical at Stanford University, University of California at Berkeley, and NTT Center Research Laboratory in Japan. He has published over 250 technical papers and 4 books on various aspects of VLSI technology and systems. His research interest includes CMOS VLSI design, semiconductor memory systems, CAD tools and circuit designs for emerging technologies including quantum MOS, spintronics, plasmonics, and resonant tunneling devices. Prof. Mazumder was a recipient of Digital's Incentives for Excellence Award, BF Goodrich National Collegiate Invention Award, DARPA Research Excellence Award, and IEEE Distinguished Lecturer. Prof. Mazumder is an AAAS Fellow (2007) and an IEEE Fellow (1999) for his distinguished contributions to the field of VLSI.