Computing - Post CMOS Era

Monday, 7 Apr 2014, 16:00 to 17:00
AG-66 (Lecture Theatre)
Abstract: With CMOS transistor technology scaling to the order of tens of nanometers, the inherent physical limitation of having only a few atoms comprise the entire transistor are beginning to surface. The reduced supply voltage of these transistors has forced researchers to encounter scenarios where operation occurs at or under the threshold voltage. In such a context computing becomes highly inefficient, both from a performance as well as a power perspective.  Attempts have been made to provide solutions to this problem both at the architecture level (heterogeneous big-LITTLE ARM architectures, near-threshold computing), as well as at the device level (low leakage transistors, vertical gate FinFETs). However, these techniques merely delay the inevitable transition to a 'Post-CMOS' technology for processor design. Under these conditions, several alternatives to CMOS have been proposed in the emerging device domain. These include several promising candidates that could complement, or even replace existing CMOS-based processors across a variety of application domains.
In this talk, I shall discuss several architectural innovations that exploit both CMOS and Post-CMOS devices to optimize performance, power and reliability. I shall describe an end-to-end methodology to abstract device characteristics into the design of a complete processor with a complete simulation infrastructure to test the veracity of these techniques. I shall also explore how this technology ties in with state of-the-art systems involving 3D stacking, domain specific accelerators and heterogeneous multi-core designs.
About the Speaker: Karthik Swaminathan was graduated from IIT Madras with a Dual Degree in Electrical Engineering. He was with IBM Research Labs, New Delhi as part of the High Performance Computing Research Group. Karthik is currently a Ph.D student in the Department of Computer Science and Engineering at the Pennsylvania State University. His research is primarily focused on power aware computer architectures and involves leveraging emerging device technologies in the architectural domain to improve performance, power and reliability.
He was awarded the prestigious IBM Ph.D Fellowship for the year 2012-2013 and has completed internships at the IBM T.J. Watson Research Center and Intel Components Research. He has several publications in top computer architecture and embedded systems conferences. He has also filed a number of patents in collaboration with industry.